PIC18F2520-I/ML【PDF 57/151 页】IC PIC MCU FLASH 16KX16 28QFN

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PIC16(L)F1782/3

DS41579C-page 324

Preliminary

2011-2012 Microchip Technology Inc.

27.1.2.8

Asynchronous Reception Set-up:

Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 27.4 “EUSART

Baud Rate Generator (BRG)”

Clear the ANSEL bit for the RX pin (if applicable).

Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

If 9-bit reception is desired, set the RX9 bit.

Enable reception by setting the CREN bit.

The RCIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RCIE interrupt enable bit was also set.

Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

27.1.2.9

9-bit Address Detection Mode Set-up

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 27.4 “EUSART

Baud Rate Generator (BRG)”).

Clear the ANSEL bit for the RX pin (if applicable).

Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

Enable 9-bit reception by setting the RX9 bit.

Enable address detection by setting the ADDEN

bit.

Enable reception by setting the CREN bit.

The RCIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the RSR to the receive buffer. An interrupt

will be generated if the RCIE interrupt enable bit

was also set.

Read the RCSTA register to get the error flags.

The ninth data bit will always be set.

10. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

device’s address.

11. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

12. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

FIGURE 27-5:

ASYNCHRONOUS RECEPTION

Start

bit

bit 7/8

bit 1

bit 0

bit 7/8

bit 0

Stop

bit

Start

bit

Start

bit

bit 7/8 Stop

bit

RX/DT pin

Reg

Rcv Buffer Reg.

Rcv Shift

Read Rcv

Buffer Reg.

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Word 1

RCREG

Word 2

RCREG

Stop

bit

Note:

This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

RCIDL

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